FTA
FAULT TREE ANALYSIS

The Fault Tree Analysis (FTA) is a analytical technique that is used for Reliability, Maintainability and Safety Analysis. An FTA attempts to integrate all factors that affect the success or failure of a product, process or mission into a single FTA Logic Diagram. The symbols used in a single FTA Logic Diagram are called Logic Gates and are similar to the symbols used by electronic circuit designers. The FTA Logic Diagram provides an elegant and precise method for defining the complex relationship that exists between the hardware, software and human components of a system.

An FTA is a status driven analysis where the inputs to a Logic Gate represent the status of a part and/or other factor being included in the analysis. Other factors can include such things as training, tools, safety equipment, supervision etc. The output from a Logic Gate is a logic state that represents a condition that exists in the system. An event occurs when the output of a Gate changes state.

If a part or other factor is functioning correctly, the state is TRUE. If the part or other factor is malfunctioning, the state is FALSE. When a logic statement is TRUE it is assigned a Boolean logic value of one (1). When a logic statement is FALSE it is assigned a Boolean logic value of zero (0). The FTA Logic Diagrams included in this analysis use the symbols listed in attached Logic Symbol Diagram. All of the rules for Boolean Algebra apply.

An FTA is performed by systematically determining what happens to the system when the status of a part or other factor changes. The minimum criteria for success is that no single failure can cause injury or an undetected loss of control over the process. Where extreme hazards exist or when high value product is being processed, the criteria may be increased to require toleration of multiple failures.

An FTA requires consideration of both positive and negative events. The logic tree segments leading to a Negative Event, such as an accident, defines all of the things that could go wrong to cause the negative event. Logic tree segments for negative events usually use more OR gates than AND gates, except for redundant safeguards.

The logic tree segment leading to a positive event defines all of the things that must work together for the machine to operate or to complete a successful mission. Logic trees for positive events generally use more AND gates than OR gates, except for redundancy. Maintenance troubleshooting trees are a good examples of logic trees for positive events. Inverting the output of a positive event converts it into a negative event.

NAND and NOR gates are used primarily to define countermeasures that, if true, will allow the system to tolerate conditions that would otherwise result in safety hazards or machine failure. Bass Associates Inc. combines Positive Events, Negative Events and Countermeasures into the FTA Logic Diagram to provide a comprehensive system analysis.

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Bass Associates Inc.
13533 Larkin Drive, Minnetonka, MN 55305
Phone: 952/544-5377


Copyright 1998 Bass Associates Inc. Last modified: June 25, 2015